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dual 12-bit, high bandwidth, multiplying dac with 4-quadrant resistors and serial interface ad5415 rev. b information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent ri ghts of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781.329.4700 www.analog.com fax: 781.461.3113? 2004C2010 analog devices, inc. all rights reserved. features 10 mhz multiplying bandwidth on-chip 4-quadrant resistors allow flexible output ranges inl of 1 lsb 24-lead tssop package 2.5 v to 5.5 v supply operation 10 v reference input 50 mhz serial interface 2.47 msps update rate extended temperature range: ?40c to 125c 4-quadrant multiplication power-on reset 0.5 a typical current consumption guaranteed monotonic daisy-chain mode readback function applications portable battery-powered applications waveform generators analog processing instrumentation applications programmable amplifiers and attenuators digitally controlled calibration programmable filters and oscillators composite video ultrasound gain, offset, and voltage trimming general description the ad5415 1 is a cmos, 12-bit, dual-channel, current output digital-to-analog converter. this device operates from a 2.5 v to 5.5 v power supply, making it suited to battery-powered appli- cations and other applications. as a result of being manufactured on a cmos submicron process, this part offers excellent 4-quadrant multiplication characteristics, with large-signal multiplying bandwidths of 10 mhz. the applied external reference input voltage (v ref ) determines the full-scale output current. an integrated feedback resistor (r fb ) provides temperature tracking and full-scale voltage output when combined with an external current-to-voltage precision amplifier. in addition, this device contains the 4-quadrant resistors necessary for bipolar operation and other configuration modes. this dac uses a double-buffered, 3-wire serial interface that is compatible with spi?, qspi?, microwire?, and most dsp interface standards. in addition, a serial data out pin (sdo) allows daisy-chaining when multiple packages are used. data readback allows the user to read the contents of the dac register via the sdo pin. on power-up, the internal shift register and latches are filled with 0s, and the dac outputs are at zero scale. the ad5415 dac is available in a 24-lead tssop package. 1 u.s. patent number 5,689,257. functional block diagram power-on reset input register dac register 12-bit r-2r dac b input register dac register 12-bit r-2r dac a shift register v dd sclk sdin gnd sdo sync ldac r3 2r r2 2r r1 2r r fb 2r r1 2r r fb 2r r3 2r r2 2r ad5415 r3a r2_3a r2a v ref a r1a r3b r2_3b r2b v ref b r1b r fb a i out 1a i out 2a i out 1b i out 2b r fb b clr 04461-001 figure 1.
ad5415 rev. b | page 2 of 32 table of contents specifications ..................................................................................... 3 timing characteristics ................................................................ 5 absolute maximum ratings ............................................................ 7 esd caution .................................................................................. 7 pin configuration and function descriptions ............................. 8 typical performance characteristics ............................................. 9 terminology .................................................................................... 14 general description ....................................................................... 15 dac section ................................................................................ 15 circuit operation ....................................................................... 15 single-supply applications ....................................................... 16 adding gain ................................................................................ 17 divider or programmable gain element ................................ 17 reference selection .................................................................... 18 amplifier selection .................................................................... 18 serial interface ............................................................................ 20 microprocessor interfacing ....................................................... 22 pcb layout and power supply decoupling ........................... 24 evaluation board for the dac ................................................. 24 power supplies for the evaluation board ................................ 24 overview of ad54xx devices ....................................................... 28 outline dimensions ....................................................................... 29 ordering guide .......................................................................... 29 revision history 4/10rev. a to rev. b added figure 4 .................................................................................. 6 7/05rev. 0 to rev. a changes to features list .................................................................. 1 change to general description ...................................................... 1 changes to specifications ................................................................ 3 changes to timing characteristics ................................................ 5 change to figure 8 and figure 9..................................................... 9 change to figure 13 ....................................................................... 10 change to figure 27 through figure 29 ..................................... 12 change to figure 32 ....................................................................... 15 changes to table 5 and table 6 ..................................................... 15 change to stability section............................................................ 16 changes to voltage-switching mode of operation section ..... 16 change to figure 35 ....................................................................... 16 changes to divider or programmable gain element section .... 17 changes to figure 36 through figure 38 .................................... 17 changes to table 7 through table 10 .......................................... 19 added adsp-bf5xx-to-ad5415 interface section ................... 22 change to 80c51/80l51-to-ad5415 interface section ............ 23 change to mc68hc11-to-ad5415 interface section .............. 23 change to power supplies for the evaluation board section ... 24 changes to table 13 ........................................................................ 28 updated outline dimensions ....................................................... 29 changes to ordering guide .......................................................... 29 7/04revision 0: initial version
ad5415 rev. b | page 3 of 32 specifications 1 v dd = 2.5 v to 5.5 v, v ref = 10 v, i out 2 = 0 v. temperature range for y version: ?40c to +125c. all specifications t min to t max , unless otherwise noted. dc performance is measured with op177, and ac performance is measured with ad8038, unless otherwise noted. table 1. parameter min typ max unit conditions static performance resolution 12 bits relative accuracy 1 lsb differential nonlinearity ?1/+2 lsb guaranteed monotonic gain error 25 mv gain error temperature coefficient 5 ppm fsr/c bipolar zero code error 25 mv output leakage current 1 na data = 0x0000, t a = 25c, i out 1 15 na data = 0x0000, t a = ?40c to +125c, i out 1 reference input reference input range 10 v v ref a, v ref b input resistance 8 10 13 k input resistance tc = ?50 ppm/c v ref a-to-v ref b input resistance mismatch 1.6 2.5 % typ = 25c, max = 125c r1, r fb resistance 17 20 25 k input resistance tc = ?50 ppm/c r2, r3 resistance 17 20 25 k input resistance tc = ?50 ppm/c r2-to-r3 resistance mismatch 0.06 0.18 % typ = 25c, max = 125c input capacitance code 0 3.5 pf code 4095 3.5 pf digital inputs/output input high voltage, v ih 1.7 v v dd = 3.6 v to 5.5 v 1.7 v v dd = 2.5 v to 3.6 v input low voltage, v il 0.8 v v dd = 2.7 v to 5.5 v 0.7 v v dd = 2.5 v to 2.7 v output high voltage, v oh v dd ? 1 v v dd = 4.5 v to 5.5 v, i source = 200 a v dd ? 0.5 v v dd = 2.5 v to 3.6 v, i source = 200 a output low voltage, v ol 0.4 v v dd = 4.5 v to 5.5 v, i sink = 200 a 0.4 v v dd = 2.5 v to 3.6 v, i sink = 200 a input leakage current, i il 1 a input capacitance 4 10 pf dynamic performance reference-multiplying bw 10 mhz v ref = 3.5 v p-p, dac loaded all 1s output voltage settling time r load = 100 , c load = 15 pf, v ref = 10 v dac latch alternately loaded with 0s and 1s measured to 1 mv of fs 80 120 ns measured to 4 mv of fs 35 70 ns measured to 16 mv of fs 30 60 ns digital delay 20 40 ns 10% to 90% settling time 15 30 ns rise and fall times digital-to-analog glitch impulse 3 nv -sec 1 lsb change around major carry, v ref = 0 v multiplying feedthrough error dac latches loaded with all 0s, v ref = 3.5 v 70 db 1 mhz 48 db 10 mhz output capacitance 12 17 pf dac latches loaded with all 0s 25 30 pf dac latches loaded with all 1s
ad5415 rev. b | page 4 of 32 parameter min typ max unit conditions digital feedthrough 3 5 nv-sec feedthrough to dac output with cs high and alternate loading of all 0s and all 1s output noise spectral dens ity 25 nv/hz @ 1 khz analog thd 81 db v ref =3. 5 v p-p, all 1s loaded, f = 1 khz digital thd clock = 10 mhz, v ref = 3.5 v 100 khz f out 61 db 50 khz f out 66 db sfdr performance (wide band) v ref = 3.5 v clock = 10 mhz 500 khz f out 55 db 100 khz f out 63 db 50 khz f out 65 db clock = 25 mhz 500 khz f out 50 db 100 khz f out 60 db 50 khz f out 62 db sfdr performance (narrow band) v ref = 3.5 v clock = 10 mhz 500 khz f out 73 db 100 khz f out 80 db 50 khz f out 87 db clock = 25 mhz 500 khz f out 70 db 100 khz f out 75 db 50 khz f out 80 db intermodulation distortion v ref = 3.5 v f 1 = 40 khz, f 2 = 50 khz 72 db clock = 10 mhz f 1 = 40 khz, f 2 = 50 khz 65 db clock = 25 mhz power requirements power supply range 2.5 5.5 v i dd 0.7 a t a = 25c, logic inputs = 0 v or v dd 0.5 10 a t a = ?40c to +125c, logic inputs = 0 v or v dd power supply sensitivity 0.001 %/% ?v dd = 5% 1 guaranteed by design and characterization, not subject to production test.
ad5415 rev. b | page 5 of 32 timing characteristics all input signals are specified with tr = tf = 1 ns (10% to 90% of v dd ) and timed from a voltage level of (v il + v ih )/2. v dd = 2.5 v to 5.5 v, v ref = 10 v, i out 2 = 0 v, temperature range for y version: ?40c to +125c. all specifications t min to t max , unless otherwise noted. table 2. parameter 1 limit at t min , t max unit conditions/comments 2 f sclk 50 mhz max maximum clock frequency t 1 20 ns min sclk cycle time t 2 8 ns min sclk high time t 3 8 ns min sclk low time t 4 13 ns min sync falling edge to sclk falling edge setup time t 5 5 ns min data setup time t 6 4 ns min data hold time t 7 5 ns min sync rising edge to sclk falling edge t 8 30 ns min minimum sync high time t 9 0 ns min sclk falling edge to ldac falling edge t 10 12 ns min ldac pulse width t 11 10 ns min sclk falling edge to ldac rising edge t 12 3 25 ns min sclk active edge to sdo valid, strong sdo driver 60 ns min sclk active edge to sdo valid, weak sdo driver update rate 2.47 msps consists of cycle time, sync high time, data setup, an d output voltage settling time 1 guaranteed by design and characterization, not subject to production test. 2 falling or rising edge as determined by the control bits of the serial word. strong or weak sdo driver selected via the contro l register. 3 daisy-chain and readback modes cannot oper ate at maximum clock frequency. sdo timing sp ecifications measured with a load circu it, as shown in figure 5. t 1 t 2 t 3 t 7 t 8 t 4 t 5 t 6 t 9 t 10 t 11 db15 db0 sclk din ldac 1 ldac 2 sync 1 asynchronous ldac update mode. 2 synchronous ldac update mode. notes alternatively, data can be clocked into the input shift register on the rising edge of sclk as determined by the control bits. timing is as above, with sclk inverted. 04461-002 figure 2. standalone mode timing diagram
ad5415 rev. b | page 6 of 32 04461-003 t 8 t 7 t 12 t 1 t 3 t 2 t 4 t 5 t 6 db15 (n) db15 (n + 1) db0 (n) db0 (n + 1) db15 (n) db0 (n) sclk sync sdin sdo notes 1. alternatively, data can be clocked into the input shift register on the rising edge of sclk as determined by the control bits. in this case, data is clocked out of sdo on the falling edge of sclk. timing is as above, with sclk inverted. figure 3. daisy-chain timing diagram sdo sdin s ync sclk 16 32 db15 db0 db15 db0 db15 undefined nop condition db0 selected register data clocked out input word specifies register to be read 04461-053 figure 4. readback mode timing diagram 200 ai ol 200 ai oh to output pin c l 50pf v oh (min) + v ol (max) 2 04461-004 figure 5. load circuit for sdo timing specifications
ad5415 rev. b | page 7 of 32 absolute maximum ratings transient currents of up to 100 ma do not cause scr latch-up. t a = 25c, unless otherwise noted. table 3. parameter rating v dd to gnd ?0.3 v to +7 v v ref , r fb to gnd ?12 v to +12 v i out 1, i out 2 to gnd ?0.3 v to +7 v input current to any pin except supplies 10 ma logic inputs and output 1 ?0.3 v to v dd + 0.3 v operating temperature range extended (y version) ?40c to +125c storage temperature range ?65c to +150c junction temperature 150c 24-lead tssop, ja thermal impedance 128c/w lead temperature, soldering (10 sec) 300c ir reflow, peak temperature (<20 sec) 235c 1 overvoltages at sclk, sync , and sdin are clamped by internal diodes. stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. esd caution esd (electrostatic discharge) sensitive device. electrostatic charges as high as 4000 v readily accumulate on the human body and test equipment and can discharge wi thout detection. although this product features proprietary esd protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. therefore, proper esd precautions are recommended to avoid performance degradation or loss of functionality.
ad5415 rev. b | page 8 of 32 pin configuration and fu nction descriptions 24 23 22 21 20 19 18 17 16 15 14 13 1 2 3 4 5 6 7 8 9 10 11 12 ad5415 top view (not to scale) sdin sclk gnd v ref a i out 1a i out 2a r fb a r1a r3a r2_3a r2a clr v dd v ref b i out 1b i out 2b r fb b r1b r3b r2_3b r2b ldac sdo sync 04461-005 figure 6. pin configuration table 4. pin function descriptions pin no. mnemonic description 1 i out 1a dac a current output. 2 i out 2a dac a analog ground. this pin should normally be tied to the analog ground of the system, but can be biased to achieve single-supply operation. 3 r fb a dac feedback resistor pin. this pin establishes voltage output for the dac by connectin g to an external amplifier output. 4 to 7 r1a, r2a, r2_3a, r3a dac a 4-quadrant resistors. these pins allow a number of configuration modes, including bipolar operation, with minimum external components. 8 v ref a dac a reference voltage input pin. 9 gnd ground pin. 10 ldac load dac input. this pin allows asynchronous or synchronous upda tes to the dac output. the dac is asynchronously updated when this sign al goes low. alternativel y, if this line is held permanently low, an automatic or synchronous update mode is selected, wher eby the dac is updated on the 16th clock falling edge when the device is in standalone mode, or on the rising edge of sync when in daisy-chain mode. 11 sclk serial clock input. by default, data is clocked into the input shift register on the falling edge of the serial clock input. alternatively, by means of the serial control bits, th e device can be configured such that data is clocked into the shift register on the rising edge of sclk. 12 sdin serial data input. data is clocked in to the 16-bit input register on the acti ve edge of the serial clock input. by default, on power-up data is clocked in to the shift register on the falling edge of sclk. the control bits allow the user to change the active edge to the rising edge. 13 sdo serial data output. this pin allows a number of parts to be daisy-chained. by default, da ta is clocked into the shift register on the falling edge and clocked out via sdo on the rising edge of sclk. data is always clocked out on the alternate edge to loading data to the shift register. writing the readback cont rol word to the shift register makes the dac register contents available for readback on the sdo pin; they are clocked out on the next 16 opposite clock edges to the active clock edge. 14 sync active low control input. this pin provides the fram e synchronization signal for the input data. when sync goes low, it powers on the sclk and sdin bu ffers, and the input shift register is en abled. data is loaded into the shift register on the active edge of the subsequent clocks. in standalone mode, the serial interface counts the clocks, and data is latched into the shift register on the 16th active clock edge. 15 clr active low control input. this pin clears the dac output, input, and dac registers. configuration mode allows the user to enable the hardware clr pin as a clear to zero scale or midscale as required. 16 v dd positive power supply input. this part can be operated from a supply of 2.5 v to 5.5 v. 17 v ref b dac b reference voltage input pin. 18 to 21 r3b, r2_3b, r2b, r1b dac b 4-quadrant resistors. these pins allow a number of configuration modes, including bipolar operation, with a minimum of external components. 22 r fb b dac b feedback resistor pin. this pin establishes vo ltage output for the dac by connecting to the external amplifier output. 23 i out 2b dac b analog ground. this pin should normally be tied to the analog ground of the system, but can be biased to achieve single-supply operation. 24 i out 1b dac b current output.
ad5415 rev. b | page 9 of 32 typical performance characteristics ?1.0 ?0.8 ?0.6 ?0.4 ?0.2 0 0.2 0.4 0.6 0.8 1.0 inl (lsb) 2000 1500 500 1000 0 2500 3000 3500 4000 code 04461-006 t a = 25c v ref = 10v v dd = 5v ?0.70 ?0.65 ?0.60 ?0.55 ?0.50 ?0.45 ?0.40 dnl (lsb) 65 34 27 8 9 reference voltage 04461-009 1 0 min dnl t a = 25c v dd = 5v figure 10. dnl vs. reference voltage figure 7. inl vs. code (12-bit dac) ?5 ?4 ?3 ?2 ?1 0 1 2 3 4 5 error (mv) ?60 ?40 ?20 0 20 40 60 80 100 120 140 temperature (c) 04461-010 v dd = 5v v dd = 2.5v v ref = 10v ?1.0 ?0.8 ?0.6 ?0.4 ?0.2 0 0.2 0.4 0.6 0.8 1.0 dnl (lsb) 2000 1500 500 1000 0 2500 3000 3500 4000 code 04461-007 t a = 25c v ref = 10v v dd = 5v figure 11. gain error vs. temperature figure 8. dnl vs. code (12-bit dac) input voltage (v) current (ma) 8 5 0 5.0 7 6 3 1 4 2 4.54.03.53.02.52.01.5 1.00.50 t a = 25 c v dd = 5v v dd = 3v v dd = 2.5v 04461-011 ?0.3 ?0.2 ?0.1 0 0.1 0.2 0.3 0.4 0.5 0.6 inl (lsb) 65 34 2 78910 reference voltage 04461-008 max inl min inl t a = 25c v dd = 5v figure 12. supply current vs. logic input voltage figure 9. inl vs. reference voltage
ad5415 rev. b | page 10 of 32 0 0.2 0.4 0.6 0.8 1.0 i out 1 leakage (na) 1.2 1.4 1.6 4020 ?20 0 ?40 60 80 100 120 temperature (c) 04461-012 i out 1 v dd = 5v i out 1 v dd = 3v figure 13. i out 1 leakage current vs. temperature 0 0.05 0.10 0.15 0.20 0.25 0.30 0.35 0.40 0.45 0.50 current ( a) ?60 ?40 ?20 0 20 40 60 80 100 120 140 temperature (c) 04461-013 v dd = 5v v dd = 2.5v all 0s all 1s all 0s all 1s figure 14. supply current vs. temperature 0 2 4 6 8 10 12 14 i dd (ma) 10k 1k 10 100 1 100k 1m 10m 100m frequency (hz) 04461-014 t a = 25c loading zs to fs v dd = 5v v dd = 3v v dd = 2.5v figure 15. supply current vs. update rate ?102 ?66 ?54 ?42 ?30 ?18 ?6 6 1 100 1k 10k 100k 1m 10m 100m frequency (hz) gain (db) t a = 25 c loading zs to fs 0 ?60 ?48 ?36 ?24 ?12 ?84 ?72 ?78 ?90 ?96 t a = 25 c v dd = 5v v ref = 3.5v c comp =1.8pf amp = ad8038 all on db11 db10 db9 db8 db7 db6 db5 db4 db3 db2 db1 db0 all off 04461-015 10 figure 16. reference multiplying bandwidth vs. frequency and code ?0.8 ?0.6 ?0.4 ?0.2 0 0.2 gain (db) 10k 1k 10 100 1 100k 1m 10m 100m frequency (hz) 04461-016 t a = 25c v dd = 5v v ref = 3.5v c comp = 1.8pf amp = ad8038 figure 17. reference multiplying bandwidthall ones loaded ?9 ?6 ?3 0 3 10k 100k 1m 10m 100m frequency (hz) t a = 25c v dd = 5v gain (db) 04461-017 v ref = 2v, ad8038 c c 1.47pf v ref = 2v, ad8038 c c 1pf v ref = 0.15v, ad8038 c c 1pf v ref = 0.15v, ad8038 c c 1.47pf v ref = 3.51v, ad8038 c c 1.8pf figure 18. reference multiplying bandwidth vs. frequency and compensation capacitor
ad5415 rev. b | page 11 of 32 ?0.010 ?0.005 0.005 0.025 0.035 0.045 0.015 0 0.020 0.030 0.040 0.010 output voltage (v) 0 20 40 60 80 100 120 140 160 180 200 time (ns) 04461-018 t a = 25c v ref = 0v amp = ad8038 c comp = 1.8pf 0x7ff to 0x800 0x800 to 0x7ff v dd = 5v v dd = 3v v dd = 3v v dd = 5v figure 19. midscale transition, v ref = 0 v output voltage (v) 0 20 40 60 80 100 120 140 160 180 200 time (ns) 04461-019 ?1.77 ?1.76 ?1.75 ?1.74 ?1.73 ?1.72 ?1.71 ?1.70 ?1.69 ?1.68 0x7ff to 0x800 0x800 to 0x7ff v dd = 5v v dd = 3v v dd = 3v v dd = 5v t a = 25c v ref = 3.5v amp = ad8038 c comp = 1.8pf figure 20. midscale transition, v ref = 3.5 v ?120 ?100 ?80 ?60 0 20 1 100 1k 10k 100k 1m 10m frequency (hz) ?40 ?20 t a = 25 c v dd = 3v amp = ad8038 full scale zero scale psrr (db) 04461-020 10 figure 21. power supply rejection ratio vs. frequency ?90 ?85 ?80 ?75 ?70 ?65 ?60 thd + n (db) 100 1k 1 10 10k 100k 1m frequency (hz) 04461-021 t a = 25c v dd = 3v v ref = 3.5v p-p figure 22. thd and noise vs. frequency 0 20 40 60 80 100 sfdr (db) 0 20 40 60 80 100 120 140 160 180 200 f out (khz) 04461-022 t a = 25c v ref = 3.5v amp = ad8038 mclk = 1mhz mclk = 200khz mclk = 0.5mhz figure 23. wideband sfdr vs. f out frequency 0 10 20 30 40 50 60 70 80 90 sfdr (db) 0 100 200 300 400 500 600 700 800 900 1000 f out (khz) 04461-023 mclk = 5mhz mclk = 10mhz mclk = 25mhz t a = 25c v ref = 3.5v amp = ad8038 figure 24. wideband sfdr vs. f out frequency
ad5415 rev. b | page 12 of 32 04461-024 ?90 ?70 ?50 ?30 ?10 sfdr (db) 0 frequency (mhz) ?80 ?60 ?40 ?20 0 t a = 25 c v dd = 5v amp = ad8038 65k codes 2 4 6 8 10 12 figure 25. wideband sfdr, f out = 100 khz, clock = 25 mhz 04461-025 ?100 ?70 ?50 ?30 ?10 sfdr (db) 0 frequency (mhz) ?80 ?60 ?40 ?20 0 t a = 25 c v dd = 5v amp = ad8038 65k codes 0.5 1.5 3.0 3.5 4.0 1.0 2.0 2.5 4.5 5.0 ?90 figure 26. wideband sfdr, f out = 500 khz, clock = 10 mhz 04461-026 ?90 ?70 ?50 ?30 ?10 sfdr (db) 0 frequency (mhz) ?80 ?60 ?40 ?20 0 0.5 1.5 3.0 3.5 4.0 1.0 2.0 2.5 4.5 5.0 t a = 25 c v dd = 5v amp = ad8038 65k codes figure 27. wideband sfdr, f out = 50 khz, clock = 10 mhz 04461-027 frequency (khz) t a = 25 c v dd = 3v amp = ad8038 65k codes ?100 ?70 ?50 ?30 ?10 sfdr (db) 250 750 300 350 400 650 700 ?80 ?60 ?40 ?20 0 ?90 450 500 550 600 figure 28. narrow-band spectral response, f out = 500 khz, clock = 25 mhz 04461-028 ?120 ?60 ?20 sfdr (db) 50 150 frequency (khz) 60 70 80 130 140 ?80 ?40 0 20 ?100 90 100 110 120 t a = 25 c v dd = 3v amp = ad8038 65k codes figure 29. narrow-band sfdr, f out = 100 khz, mclk = 25 mhz 04461-029 frequency (khz) ?100 ?70 ?50 ?30 ?10 (db) 70 120 75 80 85 115 ?80 ?60 ?40 ?20 0 ?90 90 100 105 110 t a = 25 c v dd = 3v amp = ad8038 65k codes 95 figure 30. narrow-band imd, f out = 90 khz, 100 khz, clock = 10 mhz
ad5415 rev. b | page 13 of 32 100 1k 10k 100k frequency (hz) t a = 25 c amp = ad8038 full scale loaded to dac zero scale loaded to dac 04461-031 0 50 100 150 200 250 300 output noise (nv/ hz) midscale loaded to dac 04461-030 ?100 ?40 ?20 (db) ?50 ?30 ?10 ?90 ?60 ?70 ?80 0 400 frequency (khz) 50 300 350 100 150 200 250 0 t a = 25 c v dd = 5v amp = ad8038 65k codes figure 31. wideband imd, f out = 90 khz, 100 khz, clock = 25 mhz figure 32. output noise spectral density
ad5415 rev. b | page 14 of 32 terminology relative accuracy (endpoint nonlinearity) a measure of the maximum deviation from a straight line passing through the endpoints of the dac transfer function. it is measured after adjusting for zero scale and full scale and is normally expressed in lsb or as a percentage of the full-scale reading. differential nonlinearity the difference in the measured change and the ideal 1 lsb change between two adjacent codes. a specified differential nonlinearity of ?1 lsb maximum over the operating temperature range ensures monotonicity. gain error (full-scale error) a measure of the output error between an ideal dac and the actual device output. for this dac, ideal maximum output is v ref ? 1 lsb. the gain error of the dac is adjustable to zero with an external resistance. output leakage current the current that flows into the dac ladder switches when they are turned off. for the i out 1 terminal, it can be measured by loading all 0s to the dac and measuring the i out 1 current. minimum current flows into the i out 2 line when the dac is loaded with all 1s. output capacitance capacitance from i out 1 or i out 2 to agnd. output current settling time the amount of time for the output to settle to a specified level for a full-scale input change. for this device, it is specified with a 100 resistor to ground. digital-to-analog glitch impulse the amount of charge injected from the digital inputs to the analog output when the inputs change state. this is normally specified as the area of the glitch in either pa-sec or nv-sec, depending on whether the glitch is measured as a current or voltage signal. digital feedthrough when the device is not selected, high frequency logic activity on the devices digital inputs is capacitively coupled through the device and produces noise on the i out pins and, subsequently, on the following circuitry. this noise is digital feedthrough. multiplying feedthrough error the error due to capacitive feedthrough from the dac reference input to the dac i out 1 terminal when all 0s are loaded to the dac. digital crosstalk the glitch impulse transferred to the outputs of one dac in response to a full-scale code change (all 0s to all 1s, or vice versa) in the input register of the other dac. it is expressed in nv-sec. analog crosstalk the glitch impulse transferred to the output of one dac due to a change in the output of another dac. it is measured by loading one of the input registers with a full-scale code change (all 0s to all 1s, or vice versa) while keeping ldac high and then pulsing ldac low and monitoring the output of the dac whose digital code has not changed. the area of the glitch is expressed in nv-sec. channel-to-channel isolation the portion of input signal from a dac reference input that appears at the output of another dac. it is expressed in decibels. total harmonic distortion (thd) the dac is driven by an ac reference. the ratio of the rms sum of the harmonics of the dac output to the fundamental value is the thd. usually only the lower-order harmonics are included, such as the second to fifth harmonics. 1 54 32 v vvvv thd 2222 log20 +++ = intermodulation distortion (imd) the dac is driven by two combined sine wave references of frequencies fa and fb. distortion products are produced at sum and difference frequencies of mfa nfb, where m, n = 0, 1, 2, 3 ... intermodulation terms are those for which m or n is not equal to 0. the second-order terms include (fa + fb) and (fa ? fb), and the third-order terms are (2fa + fb), (2fa ? fb), (f + 2fa + 2fb), and (fa ? 2fb). imd is defined as ( ) l fundamenta theofamplitude rms products distortion diffandsumtheofsumrms imd log20 = compliance voltage range the maximum range of (output) terminal voltage for which the device provides the specified characteristics.
ad5415 rev. b | page 15 of 32 general description dac section the ad5415 is a 12-bit, dual-channel, current output dac consisting of standard inverting r-2r ladder configuration. figure 33 shows a simplified diagram of a single channel of the ad5415. the feedback resistor r fb has a value of 2r. the value of r is typically 10 k (with a minimum of 8 k and a maximum of 12 k). if i out 1 and i out 2 are kept at the same potential, a constant current flows into each ladder leg, regardless of the digital input code. therefore, the input resistance presented at v ref is always constant. 2r s1 2r s2 2r s3 2r s12 2r dac data latches and drivers r r fb a i out 1a i out 2a v ref a 04461-032 rr r figure 33. simplified ladder access is provided to the v ref , r fb , i out 1, and i out 2 terminals of the dac, making the device extremely versatile and allowing it to be configured in several operating modes, such as unipolar output, bipolar output, or single-supply mode. circuit operation unipolar mode using a single op amp, this device can easily be configured to provide 2-quadrant multiplying operation or a unipolar output voltage swing, as shown in figure 34 . when an output amplifier is connected in unipolar mode, the output voltage is given by v out = ? v ref d /2 n where: d is the fractional representation, in the range of 0 to 4,095, of the digital word loaded to the dac. n is the number of bits. note that the output voltage polarity is opposite the v ref polarity for dc reference voltages. this dac is designed to operate with either negative or positive reference voltages. the v dd power pin is only used by the internal digital logic to drive the on and off states of the dac switches. this dac is also designed to accommodate ac reference input signals in the range of ?10 v to +10 v. with a fixed 10 v reference, the circuit in figure 34 gives a unipolar 0 v to ?10 v output voltage swing. when v in is an ac signal, the circuit performs 2-quadrant multiplication. table 5 shows the relationship between digital code and expected output voltage for unipolar operation. table 5. unipolar code digital input analog output (v) 1111 1111 1111 ?v ref (4,095/4,096) 1000 0000 0000 ?v ref (2,048/4,096) = ?v ref /2 0000 0000 0001 ?v ref (1/4,096) 0000 0000 0000 ?v ref (0/4,096) = 0 i out 1a i out 2a r fb a r fb 2r r1 2r ad5415 12-bit dac a r gnd sdin v ref a sclk sync r2 2r r3 2r r2a r2_3a r3a v dd c1 a1 v out = 0v to ?v in a gnd agnd controller agnd r1a notes 1. dac b omitted for clarity. 2. c1 phase compensation (1pf to 2pf) may be required if a1 is a high speed amplifier. 04461-033 figure 34. unipolar operation
ad5415 rev. b | page 16 of 32 bipolar operation in some applications, it may be necessary to generate full 4-quadrant multiplying operation or a bipolar output swing. this can easily be accomplished by using another external amplifier and the on-chip 4-quadrant resistors, as shown in figure 35 . when in bipolar mode, the output voltage is given by v out = ( v ref d /2 n ? 1 ) ? v ref where: d is the fractional representation, in the range of 0 to 4,095, of the digital word loaded to the dac. n is the number of bits. when v in is an ac signal, the circuit performs 4-quadrant multiplication. table 6 shows the relationship between digital code and the expected output voltage for bipolar operation. table 6. bipolar code digital input analog output (v) 1111 1111 1111 +v ref (4,095/4,096) 1000 0000 0000 0 0000 0000 0001 ?v ref (4,095/4,096) 0000 0000 0000 ?v ref (4,096/4,096) stability in the i-to-v configuration, the i out of the dac and the inverting node of the op amp must be connected as close as possible, and proper pcb layout techniques must be used. because every code change corresponds to a step function, gain peaking may occur if the op amp has limited gain bandwidth product (gbp) and there is excessive parasitic capacitance at the inverting node. this parasitic capacitance introduces a pole into the open-loop response, which can cause ringing or instability in the closed-loop applications circuit. an optional compensation capacitor, c1, can be added in parallel with r fb a for stability, as shown in figure 34 and figure 35 . too small a value of c1 can produce ringing at the output, whereas too large a value can adversely affect the settling time. c1 should be found empirically, but 1 pf to 2 pf is generally adequate for the compensation. i out 1a i out 2a r fb a r fb 2r r1 2r ad5415 12-bit dac a r gnd sdin v ref a sclk sync r2 2r r3 2r r2a r2_3a r3a v dd c1 a1 v out =?v in to +v in a1 a gnd controller r1a agnd agnd v in 04461-034 notes 1. dac b omitted for clarity. 2. c1 phase compensation (1pf to 2pf) may be required if a1 is a high speed amplifier. figure 35. bipolar operation single-supply applications voltage-switching mode of operation figure 36 shows the dac operating in the voltage-switching mode. the reference voltage, v in , is applied to the i out 1a pin, i out 2a is connected to agnd, and the output voltage is available at the v ref a terminal. in this configuration, a positive reference voltage results in a positive output voltage, making single-supply operation possible. the output from the dac is voltage at a constant impedance (the dac ladder resistance). therefore, an op amp is necessary to buffer the output voltage. the reference input no longer sees a constant input impedance, but one that varies with code. therefore, the voltage input should be driven from a low impedance source. 04461-035 v out v dd gnd v in i out 2a i out 1a r fb a v dd v ref a r 2 r 1 notes 1. similar configuration for dacb 2. c1 phase compensation (1pf to 2pf) may be required if a1 is a high speed amplifier. figure 36. single-supply voltage-switching mode note that v in is limited to low voltages because the switches in the dac ladder no longer have the same source-drain drive voltage. as a result, their on resistance differs and degrades the integral linearity of the dac. also, v in must not go negative by more than 0.3 v, or an internal diode turns on, causing the device to exceed the maximum ratings. in this type of application, the full range of multiplying capability of the dac is lost.
ad5415 rev. b | page 17 of 32 positive output voltage the output voltage polarity is opposite to the v ref polarity for dc reference voltages. to achieve a positive voltage output, an applied negative reference to the input of the dac is preferred over the output inversion through an inverting amplifier because of the resistors tolerance errors. to generate a negative reference, the reference can be level-shifted by an op amp such that the v out and gnd pins of the reference become the virtual ground and ?2.5 v, respectively, as shown in figure 37 . v dd r fb a i out 1a i out 2a c1 v out = 0 to +2.5v gnd v dd = 5v v ref a notes 1. additional pins omitted for clarity. 2. c1 phase compensation (1pf to 2pf) may be required if a1 is a high speed amplifier. 12-bit dac adr03 v out v in gnd ?5v +5v ?2.5v 04461-036 figure 37. positive voltage output with minimum of components adding gain in applications where the output voltage must be greater than v in , gain can be added with an additional external amplifier, or it can be achieved in a single stage. consider the effect of temperature coefficients of the thin film resistors of the dac. simply placing a resistor in series with the r fb resistor causes mismatches in the temperature coefficients, resulting in larger gain temperature coefficient errors. instead, the circuit in figure 38 shows the recommended method for increasing the gain of the circuit. r1, r2, and r3 should have similar temperature coefficients, but they need not match the temperature coefficients of the dac. this approach is recommended in circuits where gains of greater than 1 are required. v dd r fb a i out 1a i out 2a c1 gnd v dd v ref a notes 1. additional pins omitted for clarity. 2. c1 phase compensation (1pf to 2pf) may be required if a1 is a high speed amplifier. 12-bit dac v in r1 r3 r2 v out r1 = r2r3 r2 + r3 gain = r2 + r3 r2 04461-037 figure 38. increasing the gain of the current output dac divider or programmable gain element current-steering dacs are very flexible and lend themselves to many applications. if this type of dac is connected as the feedback element of an op amp and r fb is used as the input resistor, as shown in figure 39 , the output voltage is inversely proportional to the digital input fraction, d. for d equal to 1 ? 2 ?n , the output voltage is v out = ? v in / d = ? v in /(1 ?2 ? n ) v in notes 1. additional pins omitted for clarity. v ref a v dd v dd r fb a i out 1a i out 2a gnd v out 04461-038 figure 39. current-steering dac used as a divider or programmable gain element as d is reduced, the output voltage increases. for small values of the digital fraction, d, it is important to ensure that the amplifier does not saturate and that the required accuracy is met. for example, an 8-bit dac driven with the binary code 0x10 (0001 0000)that is, 16 decimalin the circuit of figure 39 should cause the output voltage to be 16 times v in . however, if the dac has a linearity specification of 0.5 lsb, d can have a weight in the range of 15.5/256 to 16.5/256, so that the possible output voltage is in the range of 15.5 v in to 16.5 v in an error of 3%, even though the dac itself has a maximum error of 0.2%. dac leakage current is also a potential source of errors in divider circuits. the leakage current must be counterbalanced by an opposite current supplied from the op amp through the dac. because only a fraction, d, of the current into the v ref a terminal is routed to the i out 1a terminal, the output voltage changes as follows: output error voltage due to dac leakage = ( leakage r )/ d where r is the dac resistance at the v ref a terminal. for a dac leakage current of 10 na, r = 10 k, and a gain (that is, 1/d) of 16, the error voltage is 1.6 mv.
ad5415 rev. b | page 18 of 32 reference selection when selecting a reference for use with the ad54xx series of current output dacs, pay attention to the references output voltage temperature coefficient specification. this parameter not only affects the full-scale error, but also can affect the linearity (inl and dnl) performance. the reference tempera- ture coefficient should be consistent with the system accuracy specifications. for example, an 8-bit system required to hold its overall specification to within 1 lsb over the temperature range 0c to 50c dictates that the maximum system drift with temperature should be less than 78 ppm/c. a 12-bit system with the same temperature range to overall specification within 2 lsb requires a maximum drift of 10 ppm/c. choosing a precision reference with a low output temperature coefficient minimizes this error source. table 7 lists some of the references available from analog devices that are suitable for use with this range of current output dacs. amplifier selection the primary requirement for the current-steering mode is an amplifier with low input bias currents and low input offset voltage. because of the code-dependent output resistance of the dac, the input offset voltage of an op amp is multiplied by the variable gain of the circuit. a change in this noise gain between two adjacent digital fractions produces a step change in the output voltage due to the amplifiers input offset voltage. this output voltage change is superimposed on the desired change in output between the two codes and gives rise to a differential linearity error, which, if large enough, could cause the dac to be nonmonotonic. the input bias current of an op amp also generates an offset at the voltage output as a result of the bias current flowing in the feedback resistor, r fb . most op amps have input bias currents low enough to prevent significant errors in 12-bit applications. common-mode rejection of the op amp is important in voltage-switching circuits, because it produces a code- dependent error at the voltage output of the circuit. most op amps have adequate common-mode rejection for use at 12-bit resolution. provided that the dac switches are driven from true wideband low impedance sources (v in and agnd), they settle quickly. consequently, the slew rate and settling time of a voltage- switching dac circuit is largely determined by the output op amp. to obtain minimum settling time in this configuration, minimize capacitance at the v ref node (the voltage output node in this application) of the dac. this is done by using low input capacitance buffer amplifiers and careful board design. most single-supply circuits include ground as part of the analog signal range, which in turn requires an amplifier that can handle rail-to-rail signals. analog devices offers a wide range of single-supply amplifiers, as listed in table 8 and table 9 .
ad5415 rev. b | page 19 of 32 table 7. suitable adi precision references part no. output voltage (v) initial tolerance (%) temp drift (ppm/c) i ss (ma) output noise (v p-p) package adr01 10 0.05 3 1 20 soic-8 adr01 10 0.05 9 1 20 tsot-23, sc70 adr02 5 0.06 3 1 10 soic-8 adr02 5 0.06 9 1 10 tsot-23, sc70 adr03 2.5 0.10 3 1 6 soic-8 adr03 2.5 0.10 9 1 6 tsot-23, sc70 adr06 3 0.10 3 1 10 soic-8 adr06 3 0.10 9 1 10 tsot-23, sc70 adr431 2.5 0.04 3 0.8 3.5 soic-8 adr435 5 0.04 3 0.8 8 soic-8 adr391 2.5 0.16 9 0.12 5 tsot-23 adr395 5 0.10 9 0.12 8 tsot-23 table 8. suitable adi precision op amps part no. supply voltage (v) v os (max) (v) i b (max) (na) 0.1 hz to 10 hz noise (v p-p) supply current (a) package op97 2 to 20 25 0.1 0.5 600 soic-8 op1177 2.5 to 15 60 2 0.4 500 msop, soic-8 ad8551 2.7 to 5 5 0.05 1 975 msop, soic-8 ad8603 1.8 to 6 50 0.001 2.3 50 tsot ad8628 2.7 to 6 5 0.1 0.5 850 tsot, soic-8 table 9. suitable adi high speed op amps part no. supply voltage (v) bw @ acl (m hz) slew rate (v/s) vos (max) (v) i b (max) (na) package ad8065 5 to 24 145 180 1,500 6,000 soic-8, sot-23, msop ad8021 2.5 to 12 490 120 1,000 10,500 soic-8, msop ad8038 3 to 12 350 425 3,000 750 soic-8, sc70-5 ad9631 3 to 6 320 1,300 10,000 7,000 soic-8
ad5415 rev. b | page 20 of 32 serial interface the ad5415 has an easy to use 3-wire interface that is compatible with spi, qspi, microwire, and most dsp interface standards. data is written to the device in 16-bit words. each 16-bit word consists of four control bits and 12 data bits, as shown in figure 40 . low power serial interface to minimize the power consumption of the device, the interface only powers up fully when the device is being written to, that is, on the falling edge of sync . the sclk and din input buffers are powered down on the rising edge of sync . dac control bits c3 to c0 control bits c3 to c0 allow control of various functions of the dac, as shown in table 11 . default settings of the dac at power on are as follows. data is clocked into the shift register on falling clock edges, and daisy-chain mode is enabled. the device powers on with a zero-scale load to the dac register and i out lines. the dac control bits allow the user to adjust certain features at power on. for example, daisy-chaining can be disabled when not in use, an active clock edge can be changed to a rising edge, and dac output can be cleared to either zero scale or midscale. the user can also initiate a readback of the dac register contents for verification purposes. control register (control bits = 1101) while maintaining software compatibility with single-channel current output dacs (ad5426/ad5433/ad5443), this dac also features additional interface functionality. simply set the control bits to 1101 to enter control register mode. figure 41 shows the contents of the control register, the functions of which are described in the following sections. sdo control (sdo1 and sdo2) the sdo bits enable the user to control the sdo output driver strength, disable the sdo output, or configure it as an open- drain driver. the strength of the sdo driver affects the timing of t 12 and, when stronger, allows a faster clock cycle to be used. table 10. sdo control bits sdo2 sdo1 function 0 0 full sdo driver 0 1 weak sdo driver 1 0 sdo configured as open drain 1 1 disable sdo output daisy-chain control (dsy) dsy enables or disables daisy-chain mode. a 1 enables daisy- chain mode; a 0 disables it. when disabled, a readback request is accepted, sdo is automatically enabled, the dac register contents of the relevant dac are clocked out on sdo, and, when complete, sdo is disabled again. hardware clr bit (hclr) the default setting for the hardware clr pin is to clear the registers and dac output to zero code. a 1 in the hclr bit clears the dac outputs to midscale; a 0 clears them to zero scale. active clock edge (sclk) the default active clock edge is the falling edge. write a 1 to this bit to clock data in on the rising edge; write a 0 to clock it in on the falling edge. data bits control bits c3 c2 c1 c0 db11 db10 db9 db8 db7 db6 db5 db4 db3 db2 db1 db0 db0 (lsb) db15 (msb) 04461-039 figure 40. 12-bit input shift register contents control bits 11 0 1 sdo1 sdo2 dsy hclr sclk xxxxxxx db0 (lsb) db15 (msb) 04461-040 figure 41. control register loading sequence
ad5415 rev. b | page 21 of 32 table 11. dac control bits c3 c2 c1 c0 dac function 0 0 0 0 a and b no operation (power-on default) 0 0 0 1 a load and update 0 0 1 0 a initiate readback 0 0 1 1 a load input register 0 1 0 0 b load and update 0 1 0 1 b initiate readback 0 1 1 0 b load input register 0 1 1 1 a and b update dac outputs 1 0 0 0 a and b load input registers 1 0 0 1 C disable daisy-chain 1 0 1 0 C clock data to shift register on rising edge 1 0 1 1 C clear dac output to zero scale 1 1 0 0 C clear dac output to midscale 1 1 0 1 C control word 1 1 1 0 C reserved 1 1 1 1 C no operation sync function sync is an edge-triggered input that acts as a frame synchroni- zation signal and chip enable. data can only be transferred into the device while sync is low. to start the serial data transfer, sync should be taken low, observing the minimum sync falling to sclk falling edge setup time, t 4 . daisy-chain mode daisy-chain mode is the default mode at power on. to disable the daisy-chain function, write 1001 to the control word. in daisy-chain mode, the internal gating on sclk is disabled. sclk is continuously applied to the input shift register when sync is low. if more than 16 clock pulses are applied, the data ripples out of the shift register and appears on the sdo line. this data is clocked out on the rising edge of sclk and is valid for the next device on the falling edge of sclk (default). by connecting this line to the sdin input on the next device in the chain, a multidevice interface is constructed. for each device in the system, 16 clock pulses are required. therefore, the total number of clock cycles must equal 16n, where n is the total number of devices in the chain. (see .) figure 5 when the serial transfer to all devices is complete, sync should be taken high. this prevents additional data from being clocked into the input shift register. a burst clock containing the exact number of clock cycles can be used, after which sync is taken high. after the rising edge of sync , data is automatically trans- ferred from each devices input shift register to the addressed dac. when control bits are 0000, the device is in no-operation mode. this might be useful in daisy-chain applications where the user does not want to change the settings of a particular dac in the chain. write 0000 to the control bits for that dac, and subsequent data bits are ignored. standalone mode after power on, writing 1001 to the control word disables daisy- chain mode. the first falling edge of sync resets the serial clock counter to ensure that the correct number of bits are shifted in and out of the serial shift registers. a sync edge during the 16-bit write cycle causes the device to abort the current write cycle. after the falling edge of the 16th sclk pulse, data is automati- cally transferred from the input shift register to the dac. for another serial transfer to take place, the counter must be reset by the falling edge of sync . ldac function the ldac function allows asynchronous and synchronous updates to the dac output. the dac is asynchronously updated when this signal goes low. alternatively, if this line is held per- manently low, an automatic or synchronous update mode is selected, whereby the dac is updated on the 16th clock falling edge when the device is in standalone mode, or on the rising edge of sync when the device is in daisy-chain mode. software ldac function load-and-update mode also functions as a software update function, irrespective of the voltage level on the ldac pin.
ad5415 rev. b | page 22 of 32 microprocessor interfacing microprocessor interfacing to the ad5415 dac is through a serial bus that uses standard protocol compatible with micro- controllers and dsp processors. the communication channel is a 3-wire interface consisting of a clock signal, a data signal, and a synchronization signal. the ad5415 requires a 16-bit word, with the default being data valid on the falling edge of sclk; however, this is changeable using the control bits in the data-word. adsp-21xx-to-ad5415 interface the adsp-21xx family of dsps is easily interfaced to the ad5415 dac without the need for extra glue logic. figure 42 is an example of an spi interface between the dac and the adsp-2191. sck of the dsp drives the serial data line, sdin. sync is driven from a port line, in this case spixsel . sclk sck sync spixsel sdin mosi adsp-2191 1 1 additional pins omitted for clarity. ad5415 1 04461-041 figure 42. adsp-2191 spi-to-ad5415 interface a serial interface between the dac and dsp sport is shown in figure 43 . in this interface example, sport0 is used to transfer data to the dac shift register. transmission is initiated by writing a word to the tx register after sport is enabled. in a write sequence, data is clocked out on each rising edge of the dsps serial clock and clocked into the dac input shift register on the falling edge of its sclk. the update of the dac output takes place on the rising edge of the sync signal. sclk sclk sync tfs sdin dt adsp-2101/ adsp-2103/ adsp-2191 1 1 additional pins omitted for clarity. 04461-042 ad5415 1 figure 43. adsp-2101/adsp-2103/adsp-2191 sport-to-ad5415 interface communication between two devices at a given clock speed is possible when the following specifications are compatible: frame sync delay and frame sync setup-and-hold, data delay and data setup-and-hold, and sclk width. the dac interface expects a t 4 ( sync falling edge to sclk falling edge setup time) of 13 ns minimum. see the adsp-21xx user manual for information on clock and frame sync frequencies for the sport register. table 12 shows the setup for the sport control register. table 12. sport control register setup name setting description tfsw 1 alternate framing invtfs 1 active low frame signal dtype 00 right-justify data isclk 1 internal serial clock tfsr 1 frame every word itfs 1 internal framing signal slen 1111 16-bit data-word adsp-bf5xx-to-ad5415 interface the adsp-bf5xx family of processors has an spi-compatible port that enables the processor to communicate with spi- compatible devices. a serial interface between the blackfin ? processor and the ad5415 dac is shown in figure 44 . in this configuration, data is transferred through the mosi (master output, slave input) pin. sync is driven by the spixsel pin, which is a reconfigured programmable flag pin. sclk sck sync spixsel sdin mosi adsp-bf5xx 1 1 additional pins omitted for clarity. ad5415 1 04461-052 figure 44. adsp-bf5xx-to-ad5415 interface the adsp-bf5xx processor incorporates channel synchronous serial ports (sport). a serial interface between the dac and the dsp sport is shown in figure 45 . when sport is enabled, initiate transmission by writing a word to the tx register. the data is clocked out on each rising edge of the dsps serial clock and clocked into the dacs input shift register on the falling edge of its sclk. the dac output is updated by using the transmit frame synchronization (tfs) line to provide a sync signal. sclk sclk sync tfs sdin dt adsp-bf5xx 1 1 additional pins omitted for clarity. 04461-051 ad5415 1 figure 45. adsp-bf5xx sport-to-ad5415 interface
ad5415 rev. b | page 23 of 32 80c51/80l51-to-ad5415 interface a serial interface between the dac and the 80c51 is shown in figure 46 . txd of the 80c51 drives sclk of the dac serial interface, and rxd drives the serial data line, sdin. p1.1 is a bit-programmable pin on the serial port and is used to drive sync . when data is to be transmitted to the switch, p1.1 is taken low. the 80c51/80l51 only transmits data in 8-bit bytes; therefore, only eight falling clock edges occur in the transmit cycle. to load data correctly to the dac, p1.1 is left low after the first eight bits are transmitted, and a second write cycle is initiated to transmit the second byte of data. data on rxd is clocked out of the microcontroller on the rising edge of txd and is valid on the falling edge of txd. as a result, no glue logic is required between the dac and microcontroller interface. p1.1 is taken high following the completion of this cycle. the 80c51 provides the lsb of its sbuf register as the first bit in the data stream. the dac input register requires its data with the msb as the first bit received. the transmit routine should take this into account. sclk txd 8051 1 sync p1.1 sdin rxd 1 additional pins omitted for clarity. 04461-043 ad5415 1 figure 46. 80c51/80l51-to-ad5415 interface mc68hc11-to-ad5415 interface figure 47 is an example of a serial interface between the dac and the mc68hc11 microcontroller. the serial peripheral interface (spi) on the mc68hc11 is configured for master mode (mstr) = 1, clock polarity bit (cpol) = 0, and the clock phase bit (cpha) = 1. the spi is configured by writing to the spi control register (spcr); see the 68hc11 user manual . sck of the 68hc11 drives the sclk of the dac interface; the mosi output drives the serial data line (sdin) of the dac. the sync signal is derived from a port line (pc7). when data is being transmitted to the ad5415, the sync line is taken low (pc7). data appearing on the mosi output is valid on the falling edge of sck. serial data from the 68hc11 is transmitted in 8-bit bytes with only eight falling clock edges occurring in the transmit cycle. data is transmitted msb first. to load data to the dac, leave pc7 low after the first eight bits are transferred and perform a second serial write operation to the dac. pc7 is taken high at the end of this procedure. sclk sck ad5415 1 sync pc7 sdin mosi mc68hc11 1 1 additional pins omitted for clarity. 04461-044 figure 47. mc68hc11-to-ad5415 interface if the user wants to verify the data previously written to the input shift register, the sdo line can be connected to miso of the mc68hc11, and, with sync low, the shift register clocks data out on the rising edges of sclk. microwire-to-ad5415 interface figure 48 shows an interface between the dac and any microwire-compatible device. serial data is shifted out on the falling edge of the serial clock, sk, and is clocked into the dac input shift register on the rising edge of sk, which corresponds to the falling edge of the dacs sclk. sclk sk microwire 1 sync cs sdin so ad5415 1 1 additional pins omitted for clarity. 04461-045 figure 48. microwire-to-ad5415 interface pic16c6x/7x-to-ad5415 interface the pic16c6x/7x synchronous serial port (ssp) is configured as an spi master with the clock polarity bit (ckp) = 0. this is done by writing to the synchronous serial port control register (sspcon); see the pic16/17 microcontroller user manual . in this example, i/o port ra1 is used to provide a sync signal and enable the serial port of the dac. this microcontroller transfers only eight bits of data during each serial transfer operation; therefore, two consecutive write operations are required. shows the connection diagram. figure 49 sclk sck/rc3 pic16c6x/7x 1 sync ra1 sdin sdi/rc4 ad5415 1 1 additional pins omitted for clarity. 04461-046 figure 49. pic16c6x/7x-to-ad5415 interface
ad5415 rev. b | page 24 of 32 pcb layout and power supply decoupling in any circuit where accuracy is important, careful considera- tion of the power supply and ground return layout helps to ensure the rated performance. the printed circuit board on which the ad5415 is mounted should be designed so that the analog and digital sections are separated and confined to certain areas of the board. if the dac is in a system where multiple devices require an agnd-to-dgnd connection, the connection should be made at one point only. the star ground point should be established as close as possible to the device. the dac should have ample supply bypassing of 10 f in parallel with 0.1 f on the supply located as close as possible to the package, ideally right up against the device. the 0.1 f capacitor should have low effective series resistance (esr) and low effective series inductance (esi), like the common ceramic types of capacitors that provide a low impedance path to ground at high frequencies, to handle transient currents due to internal logic switching. low esr 1 f to 10 f tantalum or electrolytic capacitors should also be applied at the supplies to minimize transient disturbance and filter out low frequency ripple. components, such as clocks, that produce fast-switching signals should be shielded with digital ground to avoid radiating noise to other parts of the board, and they should never be run near the reference inputs. avoid crossover of digital and analog signals. traces on opposite sides of the board should run at right angles to each other. this reduces the effects of feedthrough on the board. a microstrip technique is by far the best, but its use is not always possible with a double-sided board. in this technique, the component side of the board is dedicated to the ground plane, and signal traces are placed on the soldered side. it is good practice to use compact, minimum lead length pcb layout design. leads to the input should be as short as possible to minimize ir drops and stray inductance. the pcb metal traces between v ref and r fb should also be matched to minimize gain error. to maximize high frequency performance, the i-to-v amplifier should be located as close as possible to the device. evaluation board for the dac the evaluation board consists of an ad5415 dac and a current-to-voltage amplifier, the ad8065. included on the evaluation board is a 10 v reference, the adr01. an external reference can also be applied via an smb input. the evaluation kit consists of a cd-rom with self-installing pc software to control the dac. the software allows the user to write a code to the device. power supplies for th e evaluation board the board requires 12 v and +5 v supplies. the +12 v v dd and ?12 v v ss are used to power the output amplifier; the +5 v is used to power the dac (v dd1 ) and transceivers (v cc ). both supplies are decoupled to their respective ground plane with 10 f tantalum and 0.1 f ceramic capacitors.
ad5415 rev. b | page 25 of 32 v ref b u1 ad5415 p1?19 p1?20 p1?21 p1?22 p1?23 p1?24 p1?25 p1?26 p1?27 p1?28 p1?29 p1?30 v dd p2?3 p2?2 p2?1 p2?4 agnd v ss v dd 1 v dd c11 0.1 f c12 10 f c13 0.1 f c14 10 f c15 0.1 f c16 10 f + + + v dd v ss u3 c8 1.8pf c7 10 f c8 0.1 f 7 4 3 2 6 v? v+ + c9 10 f c10 0.1 f + tp1 j1 v out a v dd v ss u4 c17 1.8pf c18 10 f c19 0.1 f 7 4 3 2 6 v? v+ + c20 10 f c21 0.1 f + tp2 j2 v out b v dd 1 c2 10 f c1 0.1 f + v dd v ss u5 c22 10 f c23 0.1 f 7 4 3 2 6 v? v+ + c24 10 f c25 0.1 f + ad8065ar j3 j4 j5 j6 j7 lk1 ab r3b r2?3b i out 2b i out 1b r fb b r2b r1b v ref a r3a r2?3a r2a i out 2a i out 1a r1a r fb a gnd clr sdo ldac sync sdin sclk 3 4 1 2 5 6 7 8 21 20 22 24 23 19 18 17 16 9 11 12 14 10 13 15 clr sdo ldac sync sdin sclk r1 10k v dd 1 r2 10k v dd 1 r3 10k v dd 1 clr sdo ldac sync sdin sclk p1?2 p1?3 p1?4 p1?5 p1?13 p1?6 v dd +v in v out trim gnd c3 10 f c4 0.1 f u2 adr01ar 4 5 4 3 1 c4 0.1 f lk2 lk3 v ref j8 v in j10 a b v ref a 04461-047 figure 50. schematic of the ad5415 evaluation board
ad5415 rev. b | page 26 of 32 04461-048 figure 51. component-side artwork 04461-049 figure 52. silkscreencomponent-side view (top)
ad5415 rev. b | page 27 of 32 04461-050 figure 53. solder-side artwork
ad5415 rev. b | page 28 of 32 overview of ad54xx devices table 13. part no. resolution no. dacs inl (lsb) interface package 1 features ad5424 8 1 0.25 parallel ru-16, cp-20 10 mhz bw, 17 ns cs pulse width ad5426 8 1 0.25 serial rm-10 10 mhz bw, 50 mhz serial ad5428 8 2 0.25 parallel ru-20 10 mhz bw, 17 ns cs pulse width ad5429 8 2 0.25 serial ru-10 10 mhz bw, 50 mhz serial ad5450 8 1 0.25 serial uj-8 10 mhz bw, 50 mhz serial ad5432 10 1 0.5 serial rm-10 10 mhz bw, 50 mhz serial ad5433 10 1 0.5 parallel ru-20, cp-20 10 mhz bw, 17 ns cs pulse width ad5439 10 2 0.5 serial ru-16 10 mhz bw, 50 mhz serial ad5440 10 2 0.5 parallel ru-24 10 mhz bw, 17 ns cs pulse width ad5451 10 1 0.25 serial uj-8 10 mhz bw, 50 mhz serial ad5443 12 1 1 serial rm-10 10 mhz bw, 50 mhz serial ad5444 12 1 0.5 serial rm-8 10 mhz bw, 50 mhz serial ad5415 12 2 1 serial ru-24 10 mhz bw, 50 mhz serial ad5405 12 2 1 parallel cp-40 10 mhz bw, 17 ns cs pulse width ad5445 12 2 1 parallel ru-20, cp-20 10 mhz bw, 17 ns cs pulse width ad5447 12 2 1 parallel ru-24 10 mhz bw, 17 ns cs pulse width ad5449 12 2 1 serial ru-16 10 mhz bw, 50 mhz serial ad5452 12 1 0.5 serial uj-8, rm-8 10 mhz bw, 50 mhz serial ad5446 14 1 1 serial rm-8 10 mhz bw, 50 mhz serial ad5453 14 1 2 serial uj-8, rm-8 10 mhz bw, 50 mhz serial ad5553 14 1 1 serial rm-8 4 mhz bw, 50 mhz serial clock ad5556 14 1 1 parallel ru-28 4 mhz bw, 20 ns wr pulse width ad5555 14 2 1 serial rm-8 4 mhz bw, 50 mhz serial clock ad5557 14 2 1 parallel ru-38 4 mhz bw, 20 ns wr pulse width ad5543 16 1 2 serial rm-8 4 mhz bw, 50 mhz serial clock ad5546 16 1 2 parallel ru-28 4 mhz bw, 20 ns wr pulse width ad5545 16 2 2 serial ru-16 4 mhz bw, 50 mhz serial clock ad5547 16 2 2 parallel ru-38 4 mhz bw, 20 ns wr pulse width 1 ru = tssop, cp = lfcsp, rm = msop, uj = tsot.
ad5415 rev. b | page 29 of 32 outline dimensions 24 13 12 1 6.40 bsc 4.50 4.40 4.30 pin 1 7.90 7.80 7.70 0.15 0.05 0.30 0.19 0.65 bsc 1.20 max 0.20 0.09 0.75 0.60 0.45 8 0 seating plane 0.10 coplanarity compliant to jedec standards mo-153-ad figure 54. 24-lead thin shrink small outline package [tssop] (ru-24) dimensions shown in millimeters ordering guide model 1 resolution inl (lsb) temperature range package description package option ad5415yru 12 1 ?40c to +125c 24-lead tssop ru-24 ad5415yru-reel7 12 1 ?40c to +125c 24-lead tssop ru-24 AD5415YRUZ 12 1 ?40c to +125c 24-lead tssop ru-24 AD5415YRUZ-reel 12 1 ?40c to +125c 24-lead tssop ru-24 AD5415YRUZ-reel7 12 1 ?40c to +125c 24-lead tssop ru-24 eval-ad5415ebz evaluation kit 1 z = rohs compliant part.
ad5415 rev. b | page 30 of 32 notes
ad5415 rev. b | page 31 of 32 notes
ad5415 rev. b | page 32 of 32 notes ? 2004C2010 analog devices, inc. all rights reserved. trademarks and registered trademarks are the prop erty of their respective owners. d04461C0C4/10(b)

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